View ADV7174_1322936.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7174/adv7179 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 chip scale pal/ntsc video encoder with advanced power management functional block diagram yuv to rbg matrix video timing generator 9 9 8 10 8 8 8 10 8 8 8 10 ycrcb to yuv matrix sin/cos dds block 10 10 10 10 10 m u l t i p l e x e r i 2 c mpu port 4:2:2 to 4:4:4 inter- polator voltage reference circuit sclock sdata alsb hsync field/ vsync blank clock gnd dac a (pin 29) v ref r set comp 8 8 8 ADV7174/adv7179 10-bit dac color data p7?0 10-bit dac real-time control circuit screset/rtc inter- polator add sync programmable luminance filter 10-bit dac dac b (pin 28) dac c (pin 24) add burst inter- polator v aa y u v power management control (sleep mode) reset programmable chrominance filter cgms and wss insertion block teletext insertion block ttxreq ttx 10 10 10 u v features itu-r 1 bt601/bt656 ycrcb to pal/ntsc video encoder high quality 10-bit video dacs ssaf (super sub-alias filter) advanced power management features cgms (copy generation management system) wss (wide screen signaling) ntsc m, pal n 2 , pal b/d/g/h/i, pal 60 single 27 mhz clock required ( 2 oversampling) macrovision 7.1 (ADV7174 only) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) video input data port supports: ccir-656 4:2:2 8-bit parallel input format programmable simultaneous composite and s-video or rgb (scart)/yuv video outputs programmable luma filters (low-pass [pal/ntsc]) notch, extended ssaf, cif, and qcif programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz, and 2.0 mhz], cif and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay individual on/off control of each dac ccir and square pixel operation integrated subcarrier locking to external video source color signal control/burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c compatible and fast i 2 c) single-supply 3.3 v operation small 40-lead 6 mm 6 mm lfcsp package ?0 c to +85 c applications portable video applications g3 mobile phones digital still cameras notes 1 itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). 2 throughout the document, n is referenced to pal ?combination ?n. protected by u.s. patent numbers 5,343,196 and 5,442,355 and other intellectual property rights. protected by u.s. patent numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. the macrovision antico py process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact the sales office for the latest macrovision version available. ssaf is a trademark of analog devices, inc. i 2 c is a registered trademark of philips semiconductor.
rev. 0 ? ADV7174/adv7179?pecifications parameter conditions 1 min typ max unit static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 w 0.6 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs 3 input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 3, 4 v in = 0.4 v or 2.4 v 1 m a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 m a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 m a three-state output capacitance 10 pf analog outputs 3 output current 4, 5 r set = 150 w , r l = 37.5 w 33 34.7 37 ma output current 6 r set = 1041 w , r l = 262.5 w 5ma dac-to-dac matching 2.0 % output compliance, v oc 0 1.4 v output impedance, r out 30 k w output capacitance, c out i out = 0 ma 30 pf power requirements 3, 7 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 8 r set = 150 w , r l = 37.5 w 150 155 ma i dac (min) 8 r set = 1041 w , r l = 262.5 w 20 ma i cct 9 35 ma low power mode i dac (max) 8 80 ma i dac (min) 8 20 ma i cct 9 35 ma sleep mode i dac 10 0.1 m a i cct 11 0.001 m a power supply rejection ratio comp = 0.1 m f 0.01 0.5 %/% notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : ?0 c to +85 c. 3 guaranteed by characterization. 4 full drive into 37.5 w load. 5 dacs can output 35 ma typically at 3.3 v (r set = 150 w and rl = 37.5 w ), optimum performance obtained at 18 ma dac current (r set = 300 w and rl = 75 w ). 6 minimum drive current (used with buffered/scaled output load). 7 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 8 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 37 ma output per dac) to drive all four dacs. turning off individual dacs reduces i dac correspondingly. 9 i cct (circuit current) is the continuous current required to drive the device. 10 total dac current in sleep mode. 11 total continuous current during sleep mode. specifications subject to change without notice. 3.3 v specifications (v aa = 3.0 v?.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted.)
rev. 0 ? ADV7174/adv7179 3.3 v timing specifications (v aa = 3.0 v?.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted.) parameter conditions 1 min typ max unit mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 after this period the first clock is generated 0.6 m s setup time (start condition), t 4 relevant for repeated start condition 0.6 m s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 m s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 4, 5, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 3.5 ns data hold time, t 12 4ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 12 ns digital output hold time, t 14 4 8ns pipeline delay, t 15 48 clock cycles teletext 3, 4, 7 digital output access time, t 16 23 ns data setup time, t 17 2ns data hold time, t 18 6ns reset control 3, 4 reset low time 6 ns notes 1 the maximum/minimum specifications are guaranteed over this range. the maximum/minimum values are typical over 3.0 v to 3.6 v r ange. 2 temperature range t min to t max : ?0 c to +85 c. 3 ttl input values are 0 v to 3 v, with input rise/fall times ?3 ns, measured between the 10% and 90% points. timing reference p oints at 50% for inputs and outputs. analog output load ?10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p7?0 pixel controls: hsync , field/ vsync , blank clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx specifications subject to change without notice.
rev. 0 ADV7174/adv7179 ? t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata sclock figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync , field/ vsync , blank cb y cr y cb y hsync , field/ vsync , blank t 14 control i/ps control o/ps t 13 figure 2. pixel and control data timing diagram t 16 t 17 t 18 ttxreq clock ttx 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles figure 3. teletext timing diagram
rev. 0 ADV7174/adv7179 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7174/adv7179 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v v oltage on any digital input pin . . gnd ?0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . ?5 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . 150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 260 c analog outputs to gnd 2 . . . . . . . . . . . gnd ?0.5 v to v aa pin configurations 11 12 13 14 15 16 17 18 19 20 3 4 5 6 7 1 2 10 8 9 37 36 35 38 39 40 33 32 31 34 pin 1 identifier ADV7174/adv7179 lfcsp top view (not to scale) 26 27 28 29 24 25 22 23 21 30 v ref dac a dac b v aa gnd v aa dac c blank gnd gnd h sync field/ vsync alsb clock v aa p5 p6 p7 gnd gnd gnd gnd v aa comp sdata sclock gnd v aa gnd reset gnd p4 p3 p2 p1 p0 ttx t txreq r set screset/ rtc notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. ordering guide temperature package package model range descriptions options adv7179kcp 0 c to 70 c lfcsp lfcsp-40 adv7179bcp ?0 c to +85 c lfcsp lfcsp-40 ADV7174kcp 0 c to 70 c lfcsp lfcsp-40 ADV7174bcp ?0 c to +70 c lfcsp lfcsp-40
rev. 0 ADV7174/adv7179 e6e pin function descriptions input/ mnemonic output function p7ep0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7ep0) clock i ttl clock input. requires a stable 27 mhz reference clock for standard operation. alterna- tively, a 24.5454 mhz (nt sc) or 29.5 mhz (pal) can be u sed for square pixel operation. hsync i/o hsync (modes 1 and 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) sync signals. field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) these control signals. blank i/o video blanking control signal. the pixel inputs are ignored when this is logic level 0. this signal is optional. screset/rtc i this pin can be configured as an input by setting mr22 and mr21 of mode register 2. it can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin will reset the subcarrier to field 0. alternativel y, it may be configured as a real - time con trol (rtc) input. v ref i/o voltage reference input for dacs or voltage reference output (1.235 v) r set ia 150 w resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals. comp o compensation pin. connect a 0.1 m f capacitor from comp to v aa . for optimum dynamic performance in low power mode, the value of the comp capacitor can be lowered to as low as 2.2 nf. dac a o dac output (see table i) dac b o dac output (see table i) dac c o dac output (see table i) sclock i mpu port serial interface clock input sdata i/o mpu port serial data input/output alsb i ttl address input. this signal set up the lsb of the mpu address. reset it he input resets the on-chip timing generator and sets the ADV7174/adv7179 into default mode. this is ntsc operation, timing slave mode 0, 8-bit operation, 2 composite and s-video out, and dac b powered on and dac d powered off. ttx i teletext data ttxreq o teletext data request signal/defaults to gnd when teletext not selected v aa pp ower supply (3.3 v) gnd g ground pin
rev. 0 ADV7174/adv7179 ? general description the ADV7174/adv7179 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. the on-board ssaf (super sub-alias filter) with extended luminance frequency response and sharp stop-band attenuation enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an advanced power management circuit enables optimal control of power consumption in both normal operating modes and in power-down or sleep modes. the ADV7174/adv7179 supports both pal and ntsc square pixel operation. the parts incorporate wss and cgms-a data control generation. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync, and field timing sig nals. these timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. the encoder requires a signal two times the pixel rate (27 mhz) clock for stan dard operation. a lternatively, the encoder requires a 24.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. a separate teletext port enables the user to directly input tele text data during the vertical blanking interval. the adv71 74/adv7179 modes are set up over a 2-w ire s erial bidirectional port (i 2 c compatible) with two slave addresses. the ADV7174/adv7179 is packaged in a 40-lead lfscp package. data path description for pal b/d/g/h/i/m/n and ntsc m and n modes, ycrcb 4:2:2 data is input via the ccir-656 compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235, and cr and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb, and cr. the ADV7174/adv7179 supports pal (b/d/g/h/i/m/n) and ntsc (w ith and without pedestal) standards. the appropriate sync, blank , and burst levels are added to the ycrcb data. macrovision antitaping (ADV7174 only), closed-captioning, and teletext levels are also added to y and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is filtered and scaled by three digital fir filters. t he u and v signals are modulated by the appropriate sub- c arrier sine/cosine phases and added together to make up the chrominance signal. the luma (y) signal can be delayed 1? luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to generate rgb data with appropriate sync and blank levels. the rgb data is in synchronization with the composite video output. alternatively, analog yuv data can be generated instead of rgb data. the three l0-bit dacs can be used to output: 1. composite video + composite video 2. s-video + composite video 3. yprpb video 4. scart rgb video alternatively, each dac can be individually powered off if not required. video output levels are illustrated in appendix 6. internal filter response t he y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (ssaf) response, a cif response, and a qcif response. the uv filter supports several different frequency responses, including four low-pass responses, a cif response, and a qcif response. these can be seen in figures 4 and 5 and tpcs 1?3. filter type filter selection pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) mr04 0 0 0 0 1 1 1 mr03 0 0 1 1 0 0 1 mr02 0 1 0 1 0 1 0 low pass (ntsc) low pass (pal) notch (ntsc) notch (pal) extended (ssaf) cif qcif 0.091 0.15 0.015 0.095 0.051 0.018 monotonic 4.157 4.74 6.54 6.24 6.217 3.0 1.5 7.37 7.96 8.3 8.0 8.0 7.06 7.15 ?6 ?4 ?8 ?6 ?1 ?1 ?0 figure 4. luminance internal filter specifications filter type filter selection pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) mr07 0 0 0 0 1 1 1 mr06 0 0 1 1 0 0 1 mr05 0 1 0 1 0 1 0 1.3 mhz low pass 0.65 mhz low pass 1.0 mhz low pass 2.0 mhz low pass reserved cif qcif 0.084 monotonic monotonic 0.0645 0.084 monotonic 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 ?5 ?8.5 ?9 ?0 ?5 ?0 figure 5. chrominance internal filter specifications
ADV7174/adv7179?ypical performance characteristics 10/11/02 9:30 am jane ? rev. 0 frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 1. ntsc low-pass luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 2. pal low-pass luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 3. ntsc notch luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 4. pal notch luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 5. extended mode (ssaf) luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 6. cif luma filter
rev. 0 ADV7174/adv7179 ? frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 7. qcif luma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 8. 1.3 mhz low-pass chroma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 9. 0.65 mhz low-pass chroma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 10. 1.0 mhz low-pass chroma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 11. 2.0 mhz low-pass chroma filter frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 12. cif chroma filter
rev. 0 ADV7174/adv7179 ?0 color bar generation the ADV7174/adv7179 can be configured to generate 100/7.5/ 75/7.5 color bars for ntsc or 100/0/75/0 for pal color bars. these are enabled by setting mr17 of mode register 1 to logic 1. square pixel mode the ADV7174/adv7179 can be used to operate in square pixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accord- ingly for square pixel mode operation. color signal control the color information can be switched on and off the video output using bit mr24 of mode register 2. burst signal control the burst information can be switched on and off the video output using bit mr25 of mode register 2. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the vertical blanking interval. pixel timing description t he ADV7174/adv7179 can operate in either 8-bit or 16-bit ycrcb mode. 8-bit ycrcb mode this default mode accepts multiplexed ycrcb inputs through the p7?0 pixel inputs. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, and so on. the y, cb, and cr data are input on a rising clock edge. subcarrier reset t ogether with the screset/rtc pin, and bits mr22 and mr21 of mode register 2, the ADV7174/adv7179 can be used in subcarrier reset mode. the subcarrier will reset to field 0 at the start of the following field when a low-to-high transition occurs on this input pin. real-time control together with the screset/rtc pin, and bits mr22 and mr21 of mode register 2, the ADV7174/adv7179 can be used to lock to an external video source. the real-time control mode allows the ADV7174/adv7179 to automatically alter the s ubcarrier frequency to compensate for line length variation. when the part is connected to a device that outputs a digital d ata stream in the rtc format (such as a adv7185 video dec oder; see figure 6), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide and the subcarrier is con tained in bits 0 to 21. each bit is two clock cycles long. 00hex should be written into all four subcarrier frequency registers when using this mode. video timing description t he ADV7174/adv7179 is intended to interface with off- the- shelf mpeg1 and mpeg2 decoders. consequently, the ADV7174/adv7179 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port and has several video timing modes of operation that allow it to be configured as either a system master video timing generator or as a slave to the system video timing g enerator. the ADV7174/adv7179 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. the ADV7174/adv7179 calculates the width and placement of an alog sync pulses, blanking le vels, and color burst enve lopes. color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. in addition, the ADV7174/adv7179 supports a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections in the cor- rect location for the new clock frequencies. the ADV7174/adv7179 has four distinct master and four distinct slave timing configurations. timing control is establ ished with the bidirectional hsync , blank, and field/ vsync pins. timing mode register 1 can also be used to vary the timing p ulsewidths and where they occur in relation to each other. frequency ?mhz 0 012 2 magnitude ?db 46810 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 13. qcif chroma filter
rev. 0 ADV7174/adv7179 ?1 vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not bear line sync or pre-/post-equalization pulses (see figures 8 to 19). this mode of operation is called partial blanking and is selected by setting mr32 to 1. it allows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in the digitized incoming ycbcr data stream (e.g., wss data, cgms, vps, and so on). alternatively, the entire vbi may be blanked (no vbi data in serted) on these lines by setting mr32 to 0. composite video (e.g., vcr or cable) hsync field/ vsync clock green/luma/y red/chroma/v blue/composite/u ad7174/adv7179 p7?0 screset/rtc video decoder (e.g., adv7183a) h/ltransition count start low 128 rtc time slot: 01 14 67 68 not used in ADV7174/adv7179 19 valid sample invalid sample f sc pll increment 1 8/llc 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved notes 1 f sc pll increment is 22 bits long, value loaded into ADV7174/adv7179 fsc dds register is f sc pll increment bits 21:0 plus bits 0:9 of the subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7174/adv7179. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset ADV7174/adv7179 dds 0 figure 6. rtc timing and connections mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7174/adv7179 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. mode 0 is illustrated in figure 7. the hsync , field/ vsync, and blank (if not used) pins should be tied high during this mode.
rev. 0 ADV7174/adv7179 ?2 mode 0 (ccir-656): master option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7174/adv7179 generates h, v, and f signals required for the sav and eav time codes in the ccir-656 standard. the h bit is output on the hsync pin, the v bit is output on y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y figure 7. timing mode 0 (slave mode) 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f figure 8. timing mode 0 (ntsc master mode) the blank pin, and the f bit is output on the field/ vsync pin. mode 0 is illustrated in figure 8 (ntsc) and figure 9 (pal). the h, v, and f transitions relative to the video waveform are illustrated in figure 10.
rev. 0 ADV7174/adv7179 ?3 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 9. timing mode 0 (pal master mode)
rev. 0 ADV7174/adv7179 ?4 analog video h f v figure 10. timing mode 0 data transitions (master mode) mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode, the ADV7174/adv7179 accepts horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the ADV7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 1 is illustrated in figure 11 (ntsc) and figure 12 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank field 522 523 524 525 1 234 5 678 9 10 11 20 21 22 display display odd field even field hsync blank field vertical blank vertical blank figure 11. timing mode 1 (ntsc)
rev. 0 ADV7174/adv7179 ?5 622 623 624 625 1234 5 67 21 22 23 display odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank field display 320 vertical blank vertical blank figure 12. timing mode 1 (pal) mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode, the ADV7174/adv7179 can generate horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the ADV7174/adv7179 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the rising clock edge following the timing signal transitions. mode 1 is illustrated in figure 11 (ntsc) and figure 12 (pal). figure 13 illustrates the hsync , blank, and field for an odd or even field transition relative to the pixel data. field pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y hsync blank figure 13. timing mode 1 odd/even field transitions master/slave mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode, the ADV7174/adv7179 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7174/adv7179 automati cally blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 14 (ntsc) and figure 15 (pal).
rev. 0 ADV7174/adv7179 ?6 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank vsync vertical blank vertical blank figure 14. timing mode 2 (ntsc) 622 623 624 625 1234567 21 22 23 display odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank display 320 vsync vertical blank vertical blank figure 15. timing mode 2 (pal) mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the ADV7174/adv7179 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7174/adv7179 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 14 (ntsc) and figure 15 (pal). figure 16 illustrates the hsync , blank, and vsync for an even-to-odd field transition relative to the pixel data. figure 17 illustrates the hsync , blank, and vsync for an odd-to-even field transition relative to the pixel data.
rev. 0 ADV7174/adv7179 ?7 pal = 12 clock/2 ntsc = 16 clock/2 hsync vsync blank pixel data pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y figure 16. timing mode 2 even-to-odd field transition master/slave pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 h sync vsync b lank pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb figure 17. timing mode 2 odd-to-even field transition master/slave 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field blank field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 display display vertical blank hsync odd field blank field hsync even field figure 18. timing mode 3 (ntsc) mode 3: master/slave option hsync, blank, field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7174/adv7179 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the ADV7174/adv7179 automati- cally blanks all normally blank lines as per ccir-624. mode 3 is illustrated in figure 18 (ntsc) and figure 19 (pal).
rev. 0 ADV7174/adv7179 ?8 power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port so that the pixel inputs, p7?0, are selected. after reset, the ADV7174/ adv7179 is automatically set up to operate in ntsc mode. subcarrier frequency code 21f07c16hex is loaded into the subcarrier frequency registers. all other registers, with the exception of mode register 0, are set to 00h. with the excep tion of bit mr44, all bits in mode register 0 are set to logic level 0. bit mr44 of mode register 4 is set to logic 1. this enables the 7.5 ire pedestal. sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impos sible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error and results in very minor sch phase jumps at the start of the four- or eight-field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the ADV7174/adv7179 is con- figured in rtc mode (mr21 = 1 and mr22 = 1). under these conditions (unstable video), the subcarrier phase reset should be enabled (mr22 = 0 and mr21 = 1) but no reset ap plied. in this configuration, the sch phase will never be reset, which means that the output video will now track the unstable input video. the subcarrier phase reset, when applied, will reset the sch phase to field 0 at the start of the next field (e.g., subcarrier phase reset applied in field 5 [pal] on the start of the next field sch phase will be reset to field 0). mpu port description the ADV7174/adv7179 supports a 2-wire serial (i 2 c compat ible) microprocessor bus driving multiple peripherals. two inputs, serial da ta (sdata) and serial clock (sclock), carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7174/ adv7179 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 20 and figure 21. the lsb s ets either a read or write operation. logic level 1 corre sponds to a read operation, while logic level 0 corresponds to a write operation. a 1 is set by setting the alsb pin of the ADV7174/adv7179 to logic level 0 or logic level 1. 1 x 10101a1 address control set up by alsb read/write control 0 write 1 read figure 20. ADV7174 slave address 0 x 10 1 01a1 address control set up by alsb read/write control 0 write 1read figure 21. adv7179 slave address 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank odd field even field blank field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 hsync blank field hsync figure 19. timing mode 3 (pal)
rev. 0 ADV7174/adv7179 ?9 to control the various devices on the bus, the following protocol must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits transfer from msb down to lsb. the pe ripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an ac knowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle c ondition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte m eans that the master will read information from the peripheral. the ADV7174/adv7179 acts as a standard slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. the ADV7174/adv7179 has 26 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses?auto increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop con- dition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. there is one exception. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto increment function should then be used to increment and access subcarrier frequency registers 1, 2, and 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate j ump to the idle condition. during a given sclock high period, the user should issue only one start condition, one stop condi tion, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7174/ adv7179 will not issue an acknowledge and will return to the idle condi- ti on. if in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sdata line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7174/adv7179, and the p art will return to the idle condition. 1? 8 9 1? 8 9 1? 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure 22. bus data transfer f igure 22 illustrates an example of data transfer for a read se quence and the start and stop conditions. figure 23 shows bus write and read sequences. register accesses the mpu can write to or read from all of the ADV7174/ adv7179 registers except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all communi- cations with the part through the bus start with an access to the subaddress register. a read/write operation is performed from/ to the target address, which then increments to the next address until a stop command on the bus is performed. register programming this section describes the configuration of each register, including the subaddress register, mode registers, subcarrier frequency registers, the subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, and ntsc pedestal control registers. subaddress register (sr7?r0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 24 shows the various operations under the control of the subaddress register. zero should always be written to sr7?r6. register select (sr5?r0) these bits are set up to point to the required starting address. mode register 0 mr0 (mr07?r00) (address [sr4?r0] = 00h) figure 25 shows the various operations under the control of mode register 0. this register can be read from as well as written to. mr0 bit description output video standard selection (mr01?r00) t hese bits are used to set up the encode mode. the ADV7174/ adv7179 can be set up to output ntsc, pal (b/d/g/h/i), and pal (m and n) standard video. luminance filter control (mr02?r04) these bits specify which luma filter is to be selected. the filter s election is made independent of whether pal or ntsc is selected. figure 23. write and read sequences data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit
rev. 0 ADV7174/adv7179 ?0 sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written to these bits sr7?r6 (000) sr5 sr4 sr3 sr2 sr1 sr0 00 00 00 mo de register 0 00 00 01 mo de register 1 00 00 10 mode register 2 00 00 11 mode register 3 00 01 00 mode register 4 00 01 01 reserved 00 01 10 reserved 00 01 11 timing mode register 0 00 10 00 timing mode register 1 00 10 01 subcarrier frequency register 0 00 10 10 subcarrier frequency register 1 00 10 11 subcarrier frequency register 2 00 11 00 subcarrier frequency register 3 00 11 01 subcarrier phase register 00 11 10 closed captioning extended data byte 0 00 11 11 closed captioning extended data byte 1 01 00 00 closed captioning data byte 0 01 00 01 closed captioning data byte 1 01 00 10 ntsc pedestal control reg 0/ pal ttx control reg 0 01 00 11 ntsc pedestal control reg 1/ pal ttx control reg 1 01 01 00 ntsc pedestal control reg 2/ pal ttx control reg 2 01 01 01 ntsc pedestal control reg 3/ pal ttx control reg 3 01 01 10 cgms_wss_0 01 01 11 cgms_wss_1 01 10 00 cgms_wss_2 01 10 01 teletext request control register adv7179 subaddress regi ster sr5 sr4 sr3 sr2 sr1 sr0 ADV7174 subaddress regi ster 00 00 00 mo de register 0 00 00 01 mo de register 1 00 00 10 mo de register 2 00 00 11 mo de register 3 00 01 00 mo de register 4 00 01 01 reserved 00 01 10 reserved 00 01 11 timing mode register 0 00 10 00 timing mode register 1 00 10 01 subcarrier frequency register 0 00 10 10 subcarrier frequency register 1 00 10 11 subcarrier frequency register 2 00 11 00 subcarrier frequency register 3 00 11 01 subcarrier phase register 00 11 10 c losed captioning extended data byte 0 00 11 11 c losed captioning extended data byte 1 01 00 00 c losed captioni ng data byte 0 01 00 01 c losed captioni ng data byte 1 01 00 10 ntsc pedestal control reg 0/ pal ttx control reg 0 01 00 11 ntsc pedestal control reg 1/ pal ttx control reg 1 01 01 00 ntsc pedestal control reg 2/ pal ttx control reg 2 01 01 01 ntsc pedestal control reg 3/ pal ttx control reg 3 01 01 10 c gms _ wss_0 01 01 11 c gms _ wss_1 01 10 00 c gms _ wss_2 01 10 01 teletext request control register 01 10 10 reserved 01 10 11 reserved 01 11 00 reserved 01 11 01 reserved 01 11 10 macrovision registers 01 11 11 macrovision registers 10 00 00 macrovision registers 10 00 01 macrovision registers 10 00 10 macrovision registers 10 00 11 macrovision registers 10 01 00 macrovision registers 10 01 01 macrovision registers 10 01 10 macrovision registers 10 01 11 macrovision registers 10 10 00 macrovision registers 10 10 01 macrovision registers 10 10 10 macrovision registers 10 10 11 macrovision registers 10 11 00 macrovision registers 10 11 01 macrovision registers 10 11 10 macrovision registers 10 11 11 macrovision registers figure 24. subaddress register map chroma filter select mr07 mr06 0 0 0 1.3 mhz low-pass filter mr05 0 0 1 0.65 mhz low-pass filter 0 1 0 1.0 mhz low-pass filter 0 1 1 2.0 mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 output video standard selection mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, and i) 1 0 pal (m) 1 1 reserved luma filter select mr04 mr03 0 0 0 low-pass filter (ntsc) mr02 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 0 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved figure 25. mode register 0
rev. 0 ADV7174/adv7179 ?1 chrominance filter control (mr05?r07) these bits select the chrominance filter. a low-pass filter can be sel ected with a choice of cutoff frequencies 0.65 mhz, 1.0 mhz, 1.3 mhz, or 2 mhz, along with a choice of cif or qcif filters. mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) f igure 26 shows the various operations under the control of mode register 1. this regi ster can be read from as well as written to. mr1 bit description interlace control (mr10) this bit is used to set up the output to interlaced or noninter- laced mode. power-down mode is relevant only when the part is in composite video mode. closed captioning field selection (mr12?r11) these bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field, or both fields. dac control (mr16?r15 and mr13) these bits can be used to power down the dacs. power-down can be used to reduce the power consumption of the ADV7174/ adv7179 if any of the dacs are not required in the application. reserved (mr14) a logic 1 should be written to this register. color bar control (mr17) this bit can be used to generate and output an inte rnal color bar test pattern. the color bar configuration is 100/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled, the ADV7174/adv7179 is configured in a master timing mode. mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 closed captioning field selection 00 no data out 01 odd field only 10 even field only 11 data out (both fields) mr12 mr11 dac a control 0 normal 1p ower-down mr16 reserved dac c control mr13 dac b control mr15 interlace control 0inter laced 1nonin terlaced mr10 color bar control 0 disable 1e nable mr17 0 normal 1p ower-down 0 normal 1p ower-down 1 should be written to this bit figure 26. mode register 1 mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 chrominance control 0 enable color 1 disable color mr24 genlock control x0 disable genlock 01 enable subcarrier reset pin 11 enable rtc pin mr22 mr21 low power mode 0 disable 1 enable mr26 square pixel control 0d isable 1 enable mr20 burst control 0 enable burst 1d isable burst mr25 mr27 active video line duration 0 720 pixels 1 710 pixels/702 pixels mr23 reserved figure 27. mode register 2 mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr30 mr31 reserved vbi_open 0d isable 1 enable mr32 dac output 0 composite 1 green/luma/y mr33 dac a blue/comp/u blue/comp/u dac b red/chroma/v red/chroma/v dac c chroma output select 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr35 ttxrq bit mode control 0 normal 1 bit request mr36 input default color 0 disable 1 enable mr37 figure 28. mode register 3
rev. 0 ADV7174/adv7179 ?2 mode register 2 mr2 (mr27?r20) (address [sr4-sr0] = 02h) mode register 2 is an 8-bit-wide register. figure 27 shows the various operations under the control of mode register 2. this r egister can be read from as well as written to. mr2 bit description square pixel control (mr20) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.5454 mhz clock must be supplied. for pal, a 29.5 mhz clock must be supplied. genlock control (mr22?r21) these bits control the genlock feature of the ADV7174/adv7179. setting mr21 to logic level 1 configures the screset/rtc pin as an input. setting mr22 to logic level 0 configures the screset/rtc pin as a subcarrier reset input. therefore, the subcarrier will reset to field 0 following a low-to-high transition on the screset/rtc pin. setting mr22 to logic level 1 configures the screset/rtc pin as a real-time control input. active video line duration (mr23) this bit switches between two active video line durations. a 0 selects ccir rec601. (720 pixels pal/ntsc) and a 1 selects itu-r.bt470 standard for active video duration (710 pixels ntsc and 702 pixels pal). chrominance control (mr24) this bit enables the color information to be switched on and off the video output. burst control (mr25) this bit enables the burst information to be switched on and off the video output. low power mode (mr26) this bit enables the lower power mode of the a dv7174/adv7179. this will reduce the dac current by 45%. reserved (mr27) a logic 0 must be written to this bit. mode register 3 mr3 (mr37?r30) (address [sr4?r0] = 03h) mode register 3 is an 8-bit-wide register. figure 28 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30?r31) these bits are read-only and indicate the revision of the device. vbi open (mr32) this bit determines whether or not data in the vertical blanking i nterval (vbi) is output to the analog outputs or blanked. vbi data insertion is not available in slave mode 0. also, when both b lank input control and vbi open are enabled, blank input control has priority, i.e., vbi data insertion will not work. dac output (mr33) this bit is used to switch the dac outputs from scart to a euroscart configuration. a complete list of all dac output configurations is shown in table i. chroma output select (mr34) with this active high bit it is possible to output yuv data with a composite output on the fourth dac or a chroma output on the fourth dac (0 = cvbs; 1 = chroma). table i. dac output configuration matrix mr34 mr40 mr41 mr33 dac a dac b dac c 00 00 cvbs cvbs c 00 01 y cvbs c 00 10 cvbs cvbs c 00 11 y cvbs c 01 00 cvbs b r 01 0 1gbr 01 10 cvbs u v 01 1 1yuv 10 00 c cvbs c 10 01 y cvbs c 10 10 c cvbs c 10 11 y cvbs c 11 0 0cbr 11 0 1gbr 11 1 0cuv 11 1 1yuv cvbs: composite video baseband signal y: luminance component signal (for yuv or y/c mode) c: chrominance signal (for y/c mode) u: chrominance component signal (for yuv mode) v: chrominance component signal (for yuv mode) r: red component video (for rgb mode) g: green component video (for rgb mode) b: blue component video (for rgb mode) note each dac can be powered on or off individually with the following control bits (0 = on, 1 = off). mr13-dac c mr15-dac b mr16-dac a
rev. 0 ADV7174/adv7179 ?3 mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 output select 0 yc output 1r gb/yuv output mr40 rgb sync 0 disable 1 enable mr42 pedestal control 0 pedestal off 1 pedestal on mr44 sleep mode control 0 disable 1 enable mr46 active video filter control 0 enable 1 disable mr45 mr47 (0) zero should be written to this bit vsync _3h 0 disable 1 enable mr43 rgb/yuv control 0 rgb output 1 yuv output mr41 figure 29. mode register 4 teletext enable (mr35) this bit must be set to 1 to enable teletext data insertion on the ttx pin. ttxreq bit mode control (mr36) this bit enables switching of the teletext request signal from a continuous high signal (mr36 = 0) to a bitwise request signal (mr36 = 1). input default color (mr37) this bit determines the default output color from the dacs for zero input pixel data (or disconnected). a logic 0 means that the color corresponding to 00000000 will be displayed. a logic 1 forces the output color to black for 00000000 pixel input video data. mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) mode register 4 is an 8-bit-wide register. figure 29 shows the various operations under the control of mode register 4. mr4 bit description output select (mr40) this bit specifies if the part is in composite video or rgb/yuv mode. note that in rgb/yuv mode the composite signal is still available. rgb/yuv control (mr41) this bit enables the output from the rgb dacs to be set to yuv output video standard. rgb sync (mr42) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. vsync _3h (mr43) when this bit is enabled (1) in slave mode, it is possible to dri ve the vsync active low input for 2.5 lines in pal mode and three lines in ntsc mode. when this bit is enabled in master mode, the ADV7174/adv7179 outputs an active low vsync signal for three lines in ntsc mode and 2.5 lines in pal mode. pedestal control (mr44) this bit specifies whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid if the ADV7174/adv7179 is configured in pal mode. active video filter control (mr45) this bit controls the filter mode applied outside the active video portion of the line. this filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is sele cted. a logic 1 enables this mode. sleep mode control (mr46) when this bit is set (1), sleep mode is enabled. with this mode enabled, the ADV7174/adv7179 power consumption is reduced to typically 200 na. the i 2 c registers can be written to and read from when the ADV7174/adv7179 is in sleep mode. if mr46 is set to a (0) when the device is in sleep mode, the ADV7174/adv7179 will come out of sleep mode and resume normal operation. also, if the reset signal is applied during sleep mode, the ADV7174/adv7179 will come out of sleep mode and resume normal operation. reserved (mr47) a logic 0 should be written to this bit. tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 blank input control 0e nable 1 disable tr03 pixel port control 08 bit 1f orbidden tr06 master/slave control 0 slave timing 1m aster timing tr00 luma delay 000ns delay 0174 ns delay 10 148ns delay 11 222ns delay tr05 tr04 timing mode selection 00m ode 0 01m ode 1 10m ode 2 11m ode 3 tr02 tr01 figure 30. timing register 0
rev. 0 ADV7174/adv7179 ?4 timing mode register 0 (tr07?r00) (address [sr4?r0] = 07h) figure 30 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr0 bit description master/slave control (tr00) this bit controls whether the ADV7174/adv7179 is in master or slave mode. timing mode selection (tr02?r01) these bits control the timing mode of the ADV7174/adv7179. these modes are described in more detail in the timing specifi- cation section. blank input control (tr03) this bit controls whether the blank input is used when the part is in slave mode. luma delay (tr05?r04) these bits control the addition of a luminance delay. each bit represents a delay of 74 ns. pixel port control (tr06) t his bit is used to set the pixel port to accept 8-bit or ycrcb data on pins p7?0. timing register reset (tr07) toggling the tr07 from low to high and to low again resets the internal timing counters. this bit should be toggled after power- up, reset, or changing to a new timing mode. timing mode register 1 (tr17?r10) (address (sr4?r0) = 08h) timing register 1 is an 8-bit-wide register. figure 31 shows the various operations under the control of timing register 1. this register can be read from as well written to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr11?r10) these bits adjust the hsync pulsewidth. hsync to field/ vsync delay (tr13?r12) these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field rising edge delay (tr15?r14) when the ADV7174/adv7179 is in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. vsync width (tr15?r14) when the ADV7174/adv7179 is configured in timing mode 2, these bits adjust the vsync pulsewidth. hsync to pixel data adjust (tr17?r16) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master and slave timing modes. tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjust tr17 tr16 000 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to field/ vsync delay tr13 tr12 000 t pclk 014 t pclk 108 t pclk 11 16 t pclk t b hsync width 001 t pclk 014 t pclk 10 16 t pclk 11 128 t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 s tr15 tr14 t c vsync width (mode 2 only) tr15 tr14 001 t pclk 014 t pclk 10 16 t pclk 11 128 t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) hsync field/ vsync t a t c figure 31. timing register 1
rev. 0 ADV7174/adv7179 ?5 subcarrier frequency register 3? (fsc3?sc0) (address [sr4?r0] = 09h?ch) these 8-bit-wide registers are used to set up the subcarrier fre- quency. the value of these registers is calculated by using the following equation: subcarrier frequency register = 21 32 f f clk scf i.e.: ntsc mode, f clk = 27 mhz, f scf = 3.5795454 mhz subcarrier frequency value = 21 27 10 3 579545 10 32 6 6 . = 21f07c16 hex figure 32 shows how the frequency is set up by the four registers. subcarrier frequency reg 3 subcarrier frequency reg 2 subcarrier frequency reg 1 subcarrier frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 figure 32. subcarrier frequency register subcarrier phase register (fp7?p0) (address [sr4?r0] = 0dh) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 . for normal operation, this register is set to 00hex. closed captioning even field data register 1? (ced15?ed0) (address [sr4?r0] = 0e?fh) these 8-bit-wide registers are used to set up the closed captioning exte nded data bytes on even fields. figure 33 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced2 ced0 ced7 ced14 ced13 ced11 ced9 ced12 ced1 0 ced8 ced15 figure 33. closed captioning extended data register closed captioning odd field data register 1? (ccd15?cd0) (subaddress [sr4?r0] = 10?1h) these 8-bit-wide registers are used to set up the closed caption ing data bytes on odd fields. figure 34 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd2 ccd0 ccd7 c cd14 ccd13 ccd11 ccd9 c cd12 ccd10 ccd8 c cd15 figure 34. closed captioning data register ntsc pedestal/pal teletext control registers 3? (pce15?, pco15?)/(txe15?, txo15?) (subaddress [sr4?r0] = 12?5h) these 8-bit-wide registers are used to enable the ntsc pedes- tal/pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figures 35 and 36 show the four control registers. a logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. field 1/3 pco6 pco5 pco3 pco1 pco4 pco2 pco0 pco7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco14 pco13 pco11 pco9 pco12 pco10 pco8 pco15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 1/3 field 2/4 pce6 pce5 pce3 pce1 pce4 pce2 pce0 pce7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce14 pce13 pce11 pce9 pce12 pce1 0 pce8 pce15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 figure 35. pedestal control registers field 1/3 field 1/3 field 2/4 field 2/4 txo6 txo5 txo3 txo1 txo4 txo2 txo0 txo7 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo14 txo13 txo11 txo9 txo12 txo10 txo8 txo15 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe6 txe5 txe3 txe1 txe4 txe2 txe0 txe7 txe14 txe13 txe11 txe9 txe12 txe10 txe8 txe15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 figure 36. teletext control registers teletext request control register tc07 (tc07?c00) (address [sr4?r0] = 19h) teletext control register is an 8-bit-wide register (see figure 37). ttxreq rising edge control (tc07?c04) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles (see figure 37). ttxreq falling edge control (tc03?c00) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increasing this value reduces the amount of teletext bits below the default of 360. if bits tc03-tc00 are 00hex when bits tc07?c04 are changed, the falling edge of ttxreq will track that of the rising edge, i.e., the time between the falling and rising edge remains constant, (see figure 37). cgms_wss register 0 c/w0 (c/w07?/w00) (address [sr4?r0] = 16h) cgms_wss register 0 is an 8-bit-wide register. figure 38 shows the operations under the control of this register.
rev. 0 ADV7174/adv7179 ?6 c/w0 bit description cgms data bits (c/w03?/w00) these four data bits are the final four bits of the cgms data output stream. note it is cgms data only in these bit posi- tions, i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, are calculated internally by the ADV7174/adv7179. if this bit is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd fields. note this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even fields. note this is only valid in ntsc mode. wss control (c/w07) when this bit is set (1), wide screen signaling is enabled. note this is only valid in pal mode. cgms_wss register 1 c/w1 (c/w17?/w10) (address [sr4?r0] = 17h) cgms_wss register 1 is an 8-bit-wide register. figure 39 shows the operations under the control of this register. c/w1 bit description cgms/wss data bits (c/w15?/w10) these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data. cgms data bits (c/w17?/w16) these bits are cgms data bits only. cgms_wss register 2 c/w1 (c/w27?/w20) (address [sr4?r0] = 18h) cgms_wss register 2 is an 8-bit-wide register. figure 40 shows the operations under the control of this register. c/w2 bit description cgms/wss data bits (c/w27?/w20) these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data. tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 00 00 0 pclk 00 01 1 pclk "" "" " pclk 11 10 14 pclk 11 11 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 00 00 0 pclk 00 01 1 pclk "" "" " pclk 11 10 14 pclk 11 11 15 pclk figure 37. teletext control register c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 c/w07 wide screen signal control 0d isable 1 enable 0d isable 1 enable c/w05 cgms odd field control c/w06 cgms even field control 0d isable 1 enable c/w04 cgms crc check control 0d isable 1 enable c/w03 ?c/w00 cgms data bits figure 38. cgms_wss register 0 c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 ?c/w10 cgms/wss data bits c/w17 ?c/w16 cgms data bits figure 39. cgms_wss register 1 c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27 ?c/w20 cgms/wss data bits figure 40. cgms_wss register 2
rev. 0 ADV7174/adv7179 ?7 t he ADV7174/adv7179 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system-level design so that high speed, accurate performance is achieved. figure 41, recommended analog circuit layout, shows the analog interface between the device and monitor. the layout should be optimized for lowest no ise on the ADV7174/ adv7179 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should be minimized to mini mize induc tive ringing. ground planes the ground plane should encompass all ADV7174/adv7179 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7174/adv7179, the analog output traces, and all the digital signal traces leading up to the ADV7174/ adv7179. the ground plane is the board? common ground plane. power planes the ADV7174/adv7179 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within 3 inches of the ADV7174/adv7179. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all ADV7174/ adv7179 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common mode. appendix 1 board design and layout considerations supply decoupling for optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera tion, to reduce the lead inductance. best performance is obtained with 0.1 m f ceramic capacitor decoupling. each group of v aa pins on the ADV7174/adv7179 must have at least one 0.1 m f decoupling capacitor to gnd. these capacitors should be placed as close to the device as possible. it is important to note that while the ADV7174/adv7179 contains circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage r egulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the ADV7174/adv7179 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the ADV7174/adv7179 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not to the analog power plane. analog signal interconnect the ADV7174/adv7179 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, s hould never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 w load resistor connected to gnd. these resistors should be placed as close as possible to the ADV7174/adv7179 to minimize reflections. the ADV7174/adv7179 should have no inputs left floating. any inputs that are not required should be tied to ground.
rev. 0 ADV7174/adv7179 ?8 5k +3.3 v (v cc ) 150 5k +3.3 v (v cc ) mpu bus 3?, 35?9 0.1 f 0.01 f 0.1 f +3.3 v (v aa ) 0.1 f +3.3v (v aa ) 10k +3.3 v (v aa ) 27mhz clock (same clock as used by mpeg2 decoder) power supply decoupling for each power supply group 10 f 33 f gnd l1 (ferrite bead) +3.3 v gnd alsb hsync field/ vsync blank reset clock r set sdata sclock dac b dac c v aa v ref comp p7?0 +3.3 v (v aa ) 75 75 75 screset/rtc ADV7174/adv7179 unused inputs should be grounded dac a 100 100 r eset ttx ttxreq (v cc ) 100k 100k +3.3 v (v cc ) ttx ttxreq teletext pull-up and pull-down resistors should only be used if these pins are not connected 24 28 29 22 1 20 13 15 14 16 21 31 23 30 4k +3.3 v (v aa ) 100nf 32 34 33 figure 41. recommended analog circuit layout the circuit below can be used to generate a 13.5 mhz waveform using the 27 mhz clock and the hsync pulse. this waveform is guaranteed to produce the 13.5 mhz clock in synchronization with the 27 mhz clock. this 13.5 mhz clock can be used if d q ck d q ck clock hsync 13.5mhz figure 42. circuit to generate 13.5 mhz the 13.5 mhz clock is required by the mpeg decoder. this guarantees that the cr and cb pixel information is input to the ADV7174/adv7179 in the correct sequence.
rev. 0 ADV7174/adv7179 ?9 the ADV7174/adv7179 supports closed captioning, conforming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency-locked and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. 16 bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the ADV7174/adv7179 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are automatically generated by the ADV7174/ adv7179. all pixel inputs are ignored during lines 21 and 284. appendix 2 closed captioning fcc code of federal regulations (cfr) 47 section 15.119 and eia-608 describe the closed captioning information for lines 21 and 284. the ADV7174/adv7179 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which will in turn load the new data (two bytes) every field. if no new data is required for transmission, you must insert zeros in both the data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21, or a tv will not recognize them. if you have a message such as ?ello world,?which has an odd number of characters, it is important to pad it out to an even number to get the end of caption 2-byte control code to land in the same field. 12.91 s s t a r t p a r i t y p a r i t y d0?6 d0?6 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 figure 43. closed captioning waveform (ntsc)
rev. 0 ADV7174/adv7179 ?0 the ADV7174/adv7179 supports the copy generation m anage- ment system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and on line 283 of the even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the ADV7174/adv7179 is configured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is pre ceded by a reference pulse of the same amplitude and duration as a cgms bit (see figure 44). the bits are output from the configuration registers in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/ w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c12, c/ w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/ w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if bit c/w04 is set to a logic 1, the last six bits, c19?14, which comprise the 6-bit crc check sequence, are calculated automatically on the ADV7174/adv7179 based on the lower 14 bits (c0c13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calcu- lation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0?19) are directly output from the cgms regis ters (no crc is calculated; it must be calculated by the user). function of cgms bits word 0? bits word 1? bits word 2? bits crc? bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:94:3 b2 display format letterbox normal b3 undefined word 0 b4, b5, b6 identification information about video and other signals (e.g., audio) word 1 b7, b8, b9, b10 identification signal incidental to word 0 word 2 b11, b12, b13, b14 identification signal and information incidental to word 0 crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire ?0 ire figure 44. cgms waveform diagram appendix 3 copy generation management system (cgms)
rev. 0 ADV7174/adv7179 ?1 the ADV7174/adv7179 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the ADV7174/ adv7179 is configured in pal mode. the wss data is 14 bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 45). the bits are output from the configuration registers in the following order: c/w20 = w0, c/w21 = w1, c/ w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a logic 1, it enables the wss data to be trans- mitted on line 23. the latter portion of line 23 (42.5 m s from the falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0?it 2 aspect ratio/format/position bit 3 is odd parity check of bit 0?it 2 b0 b1 b2 b3 aspect ratio format position 000 1 4:3 full format nonapplicable 100 0 14:9 letterbox center 010 0 14:9 letterbox top 110 1 16:9 letterbox center 001 0 16:9 letterbox top 101 1 >16:9 letterbox center 011 1 14:9 full format center 111 0 16:9 non applicable non applicable b4 b9 b10 0c amera mode 0 0 no open subtitles 1f ilm mode 1 0 subtitles in active image area b5 0 1 subtitles out of active image area 0 standard coding 1 1 reserved 1m otion adaptive color plus b11 b6 0 no surround sound information 0n o helper 1 surround sound mode 1m odulated helper b12 reserved b7 reserved b13 reserved 11.0 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s figure 45. wss waveform diagram appendix 4 wide screen signaling
rev. 0 ADV7174/adv7179 ?2 t pd is the time needed by the ADV7174/adv7179 to interpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t synttxout = 10.2 m s after the leading edge of the horizontal signal. time ttx del is the pipeline delay time by the source that is gated by the ttxreq signal in order to deliver ttx data. with the programmability offered with the ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 m s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipe line delays. the width of the ttxreq signal must always be maintained to allow the insertion of 360 (to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mb its/s. this is achieved by setting tc03?c00 to zero. the inser- tion w indow is not open if the teletext enable bit (mr35) is set to zero. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is as follows: 27 4 6 75 6 9375 10 6 75 10 1 027777 66 mhz mhz () = () = . ... thus, 37 ttx bits correspond to 144 clocks (27 mhz) and each bit has a width of almost four clock cycles. the ADV7174/ adv7179 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus gen- erate a band-limited signal that can be output on the cvbs and y outputs. at the ttx input, the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bits 10, 19, 28, and 37 are carried by three clock cycles and all other bits by four clock cycles. after 37 ttx bits, the next bits with three clock cycles are 47, 56, 65, and 74. this scheme holds for all following cycles of 37 ttx bits until all 360 ttx bits are completed. all teletext lines are implemented in the same way. individual control of teletext lines is controlled by teletext setup registers. address and data run-in clock teletext vbi line 45 bytes (360 bits) ?pal figure 46. teletext vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t synttxout = 10.2 s t pd = pipeline delay through adv7170/adv7171 ttx del = ttxreq to ttx (programmable range = 4 bits [0?5 clock cycles]) t synttxout 10.2 s ttx del ttx st figure 47. teletext functionality appendix 5 teletext insertion
rev. 0 ADV7174/adv7179 ?3 appendix 6 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire ?0 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 48. ntsc composite video levels 100 ire 7.5 ire 0 ire ?0 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 49. ntsc luma video levels 650mv 335.2mv 963.8mv 0mv peak chroma blank /black level 286mv (p-p) 629.7mv (p-p) peak chroma figure 50. ntsc chroma video levels 100 ire 7.5 ire 0 ire ?0 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 51. ntsc rgb video levels
rev. 0 ADV7174/adv7179 ?4 ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire ?0 ire peak composite ref white sync level blank /black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 52. ntsc composite video levels 100 ire 0 ire ?0 ire ref white sync level blank /black level 714.2mv 1052.2mv 338mv 52.1mv figure 53. ntsc luma video levels 650mv 299.3mv 978mv 0mv peak chroma blank /black level 286mv (p-p) peak chroma 694.9mv (p-p) figure 54. ntsc chroma video levels 100 ire 0 ire ?0 ire ref white sync level blank /black level 715.7mv 1052.2mv 336.5mv 51mv figure 55. ntsc rgb video levels
rev. 0 ADV7174/adv7179 ?5 pal waveforms 650mv 317.7mv 989.7mv 0mv peak chroma blank /black level 300mv (p-p) 672mv (p-p) peak chroma figure 56. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank /black level 696.4mv figure 57. pal luma video levels 650mv 317.7mv 989.7mv 0mv peak chroma blank /black level 300mv (p-p) 672mv (p-p) peak chroma figure 58. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank /black level 698.4mv figure 59. pal rgb video levels
rev. 0 ADV7174/adv7179 ?6 betacam level 0mv +171mv +334mv +505mv 0mv ?71mv ?34mv ?5mv white yellow cyan green magenta red blue black figure 60. ntsc 100% color bars, no pedestal u levels betacam level 0mv +158mv +309mv +467mv 0mv ?58mv ?09mv ?67mv white yellow cyan green magenta red blue black figure 61. ntsc 100% color bars with pedestal u levels smpte level 0mv +118mv +232mv +350mv 0mv ?18mv ?32mv ?50mv white yellow cyan green magenta red blue black figure 62. pal 100% color bars, u levels uv waveforms betacam level 0mv +82mv +423mv +505mv 0mv ?2mv ?05mv ?23mv white yellow cyan green magenta red blue black figure 63. ntsc 100% color bars, no pedestal v levels betacam level 0mv +76mv +391mv +467mv 0mv ?6mv ?67mv ?91mv white yellow cyan green magenta red blue black figure 64. ntsc 100% color bars with pedestal v levels smpte level 0mv +57mv +293mv +350mv 0mv ?7mv ?50mv ?93mv white yellow cyan green magenta red blue black figure 65. pal 100% color bars, v levels
rev. 0 ADV7174/adv7179 ?7 appendix 7 optional output filter if an output filter is required for the cvbs, y, uv, chroma and rgb outputs of the ADV7174/adv7179, the filter shown in figure 66 can be used. plots of the filter characteristics are shown in figure 67. an output filter is not required if the outputs 1.8 h 75 270pf 22pf 330pf filter i/p filter o/p 75 figure 66. output filter of the ADV7174/adv7179 are connected to most analog monitors or analog tvs. however, if the output signals are applied to a system where sampling is used (e.g., digital tvs), then a filter is required to prevent aliasing. frequency ?hz 0 80 100k magnitude ?db 70 60 50 40 30 20 10 1m 10m 100m figure 67. output filter plot
rev. 0 ADV7174/adv7179 ?8 appendix 8 optional dac buffering when external buffering is needed of the ADV7174/adv7179 dac outputs, the configuration in figure 68 is recommended. this configuration shows the dac outputs running at half (18 ma) of their full current (36 ma) capability. this will allow the ADV7174/adv7179 to dissipate less power; the analog current is reduced by 50% with a r set of 300 and a r load of 75 . this mode is recommended for 3.3 v operation as opti- mum performance is obtained from the dac outputs at 18 ma with a v aa of 3.3 v. this buffer also adds extra isolation on the video outputs (see buffer circuit in figure 69). when calculating absolute output full-scale current and voltage, use the following equations: vir i (v k) r k. constant, v . v out out load out ref set ref = = == 4 2146 1 235 ADV7174/adv7179 v ref digital core pixel port 300 r set v aa output buffer dac a output buffer output buffer dac c dac b cvbs luma cvbs output filter output filter output filter figure 68. output buffering configuration ad8061 75 1 3 2 video input video output 1.2k 75 r 1 r 3 1.2k r 2 figure 69. recommended output dac buffering
rev. 0 ADV7174/adv7179 ?9 appendix 9 recommended register values the ADV7174/adv7179 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case, the output is set to composite o/p with all dacs powered up and with the blank input control disabled. additionally, the burst and color information is enabled on the output, and the internal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02?r00 of the timing register 0 control the timing modes. for a detailed explanation of each bit in the command registers, please turn to the register programming section of the data sheet. tr07 should be toggled after setting up a new timing mode. timing register 1 provides additional control over the position and duration of the timing signals. in the examples, this register is programmed in default mode. pal b/d/g/h/i (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 10hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext request control register 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 10hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex pal-60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 04hex 01hex mode register 1 10hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex
rev. 0 ADV7174/adv7179 ?0 pal-60 (continued) (f sc = 4.43361875 mhz) address data 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex power-up reset values ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 00hex 01hex mode register 1 10hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 10hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 16hex 0ahex subcarrier frequency register 1 7chex 0bhex subcarrier frequency register 2 f0hex 0chex subcarrier frequency register 3 21hex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss reg 0 00hex 17hex cgms_wss reg 1 00hex 18hex cgms_wss reg 2 00hex 19hex teletext request control register 00hex
rev. 0 ADV7174/adv7179 ?1 outline dimensions 40-lead frame chip scale package [lfcsp] (cp-40) dimensions shown in millimeters 1 40 10 11 31 30 21 20 bottom view 4.25 3.70 sq 1.75 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.25 ref seating plane 1.00 0.90 0.80 0.05 max 0.02 nom coplanarity 0.08 0.70 max 0.65 nom 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max compliant to jedec standards mo-220-vjjd-2
?2
?3
?4 c02980??0/02(0) printed in u.s.a.

▲Up To Search▲

Price & Availability of ADV7174

	To Download ADV7174 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .